With the gradual increase in integration of semiconductor devices, much effort has been dedicated to planarization processes to planarize an insulating layer, such as an interlayer insulating layer formed on a semiconductor substrate. Recently, STI process known as (Shallow Trench Isolation) has been widely used to electrically isolate device elements on a semiconductor substrate on the behalf of LOCOS process, and increase in step between the device elements requires a variety of planarization techniques.
There have been several processes used to planarize insulating layers, for example, BPSG (Boron Phosphorus Silicate Glass) reflow, SOG (Spin On Glass) or photoresist etch back, and CMP (Chemical Mechanical Polishing). Particularly, CMP can be used to planarize a wider area in comparison with the other processes, and can be performed at a low temperature. Because of these advantages, CMP has come into wide use in substrate planarization. A typical CMP process is disclosed in, for example, U.S. Pat. No. 5,064,683, issued Feb. 27, 1996.
However, substrate planarization using CMP leads to three main problems: first, in a substrate structure having dish-shape, a dishing phenomenon is generated. Second, the substrate is contaminated by a polishing slurry. Third, the substrate and the CMP planarizing apparatus are contaminated by particles generated during the CMP process.